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OKI Semiconductor ML674000
32-bit General-purpose, ARM-based Microcontroller
FEDL674000-02
Issue Date: Dec. 10, 2002
GENERAL DESCRIPTION
Oki's ML674000 standard microcontroller (MCU) is a member of an extensive and growing family of ARM(R) architecture 32-bit MCUs for general-purpose applications that require 32-bit CPU performance and low cost afforded by MCU integrated features. ML674000 MCU provides a host of useful peripherals such as 8KB of on-board SRAM, timers, watchdog timer, pulse-width modulators, AD converter, UART's, GPIO connectivity capability, and external memory controller. These integrated features make it ideal for embedded applications where low costs and low power consumption are key. Oki's ML674K series MCUs are capable of executing both the 32-bit ARM instruction set for high-performance applications as well as the 16-bit Thumb(R) instruction set for power-efficient applications. With an ARM7TDMI(R) core operating at 33 MHz maximum frequency, ARM ThumbTM capabilities, and robust feature sets, the ML674K series MCUs are suitable for an array of applications including high performance industrial controllers and instrumentation, telecom, PC peripherals, security/surveillance, test equipment, and a variety of consumer electronics devices. The ARM7TDMI(R) Advantage Oki's ML67 Family of low-cost ARM-based MCUs offers system designers a bridge from 8- and 16-bit proprietary MCU architectures to ARM's higher-performance, affordable, widely-accepted industry standard architecture and its industry-wide support infrastructure. The ARM industry infrastructure offers system developers many advantages including software compatibility, many ready-to-use software applications, and numerous choices among hardware and software development tools. These ARM-based advantages allow Oki's customers to better leverage engineering resources, lower development costs, minimize project risks, and reduce their product time to market. In addition, migration of a design with an Oki standard MCU to an Oki custom solution is easily facilitated with its award-winning PLATTM product development architecture.
FEATURES
* CPU 32-bit RISC CPU (ARM7TDMI) 32-bit instructions (ARM Instructions) and 16-bit instructions (Thumb Instructions) mixed General purpose registers : 31 x 32 bits Built-in Barrel shifter and multiplier (32 bit x 8 bit, Modified Booth's Algorithm) Little endian Built-in debug function Internal memory RAM 8KB (32-bit access) External memory controller ROM (FLASH): 16 Mbytes SRAM: 16 Mbytes DRAM: 64 Mbytes (SDRAM and EDO-DRAM support) External IO devices: 16 Mbytes x 2 banks (with wait control by external signal)
* *
ARM, ARM7TDMI, Multi-ICE and AMBA are registered trademarks of ARM Ltd., UK. PLAT is Oki's trademark. The contents of this data sheet are subject to change for modification without notice.
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ML674000
* * *
* * * * * * * * * *
Interrupt controller 24 sources: 19 internals and 5 externals (IRQ: 4, FIQ: 1) DMA controller 2 channels: Dual address mode, cycle steal and burst tranfer mode Timer 1 channel: 16-bit auto reload for operating system 6 channels: 16-bit auto reload for application 1 channel: 16 bit watchdog timer Serial interface 1 channel: UART 1 channel: UART with 16-byte FIFO Parallel I/O Port 2 ports x 16 bits (bitwise input/output settings) PWM 2 channels x 16 bits Analog-to-Digital Converter 8 channels x 10 bits Power down mechanism Standby (all clock stop) and Halt (clock stop by each function block) Clock gear (selectable 1/1, 1/2, 1/4, 1/8, 1/16 input clock frequency) JTAG interface Connectable to JTAG ICE (e.g. ARM MutiICE) Power supply voltage Core section: 2.25 V to 2.75 V IO section: 3.0 V to 3.6 V Operating frequency 33 MHz (Max.) Operating temperature (ambient temperature) -40C to +85C Package 128-pin plastic TQFP (P-TQFP128-1414-0.40-K) 144-pin plastic LFBGA (P-LFBGA144-1111-0.80)
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ML674000
BLOCK DIAGRAM
TDI TDO nTRST TMS TCK TBE DBGRQ DBGACK PIOA[14:10]/XA[23:19] XA[18:0] XD[15:0] PIOA[15]/XWR XOE_N XBWE_N[1:0] XROMCS_N XRAMCS_N XIOCS_N[0] XIOCS_N[1] XBS_N[1:0] PIOB[8]/XWAIT PIOB[9]/XCAS_N PIOB[10]/XRAS_N PIOB[11]/XSDCLK PIOB[12]/XSDCS_N PIOB[13]/XSDCKE PIOB[14]/ XDQM[1]/XCAS_N[1] PIOB[15]/ XDQM[0]/XCAS_N[0]
Internal RAM 8KB 8
PLAT-7B
ARM7TDMI
Internal & External Memory controller
TIC AHB Bridge
AMBA AHB bus
DRAMC
APB Bridge
AMBA APB bus
IRC
Ext. IRC APB Bridge
APB bus
DMAC
2 2 2
PIOB[0]/DREQ[0] PIOB[2]/DREQ[1] PIOB[1]/DREQCLR[0] PIOB[3]/DREQCLR[1] PIOB[4:5]/TCOUT[1:0]
System TMR
SIO
System Control
16 bit x 6ch 16 bit x 2ch
WDT CGB UART (16550) 8 PWM 2 PIOB[7:6]/PWMOUT[1:0] PIOA[0]/SIN PIOA[1]/SOUT PIOA[2]/CTS PIOA[3]/DSR PIOA[4]/DCD PIOA[5]/DTR PIOA[6]/RTS PIOA[7]/RI AIN[7:0] VREF
TMR
RESET_N PIOA[8]/STXD PIOA[9]/SRXD OSC0 OSC1_N
A/D 1 EFIQ_N EXINT[3:0] VDD_CORE GND_CORE VDD_IO GND_IO AVDD AGND MODE[2:0] 4 GPIO
9
32
PIOA[15:0] PIOB[15:0]
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PIN CONFIGURATION (TOP VIEW)
(Secondary function)
XA[23] XA[22]
PIOA[14] PIOA[13] VDD_IO PIOA[12] PIOA[11] PIOA[10] XA[18] GND_IO XA[17] XA[16] XA[15] XA[14] XA[13] VDD_CORE GND_CORE XA[12] XA[11] XA[10] XA[9] VDD_IO GND_IO XA[8] XA[7] XA[6] XA[5] XA[4] XA[3] XA[2] XA[1] XA[0]
(Primary function)
XA[21] XA[20] XA[19]
(Secondary function) XWR
(Primary function) PIOA[15] XOE_N XWE_N GND_IO XBWE_N[0] XBWE_N[1] XROMCS_N XRAMCS_N XIOCS_N[0] XIOCS_N[1] GND_CORE VDD_CORE PIOB[0] PIOB[1] VDD_IO PIOB[2] PIOB[3] PIOB[4] PIOB[5] GND_IO PIOB[6] PIOB[7] XBS_N[0] XBS_N[1] PIOB[8] PIOB[9] PIOB[10] PIOB[11] PIOB[12] PIOB[13] VDD_IO GND_IO 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
GND_IO XD[15]
(Primary function) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 XD[14] XD[13] XD[12] VDD_IO XD[11] XD[10] XD[9] XD[8] GND_IO XD[7] XD[6] XD[5] XD[4] XD[3] XD[2] XD[1] XD[0] VDD_CORE OSC1_N OSC0 GND_CORE GND_IO RESET_N EFIQ_N EXINT3 EXINT2 EXINT1 EXINT0 PIOA[9] PIOA[8] MODE[2] MODE[1]
(Secondary function)
DREQ0 DREQCLR0 DREQ1 DREQCLR1 TCOUT0 TCOUT1 PWMOUT0 PWMOUT1
XWAIT XCAS_N XRAS_N XSDCLK XSDCS_N XSDCKE
SRXD STXD
(Primary function)
PIOB[14] PIOB[15] DBGRQ DBGACK TDI TDO nTRST TMS TCK TBE PIOA[0] PIOA[1] PIOA[2] PIOA[3] PIOA[4] PIOA[5] PIOA[6] PIOA[7] GND_CORE VDD_CORE AVDD VREF AIN[0] AIN[1] AIN[2] AIN[3] AIN[4] AIN[5] AIN[6] AIN[7] XDQM[1]/XCAS_N[1] XDQM[0]/XCAS_N[0]
(Secondary function)
128-Pin Plastic TQFP
SIN SOUT CTS DSR DCD DTR RTS RI
AGND MODE[0]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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ML674000
A 13
NC
B
NC
C
NC
D
PIOA[12]/ XA[21]
E
XA[18]
F
XA[16]
G
GND_ CORE
H
XA[8]
J
XA[5]
K
XA[2]
L
GND_IO
M
XD[15]
N
NC
13
12
PIOA[15]/ XWR
PIOA[14]/ XA[23]
VDD_IO
GND_IO
XA[15]
XA[14]
XA[10]
GND_IO
XA[7]
XA[4]
XA[1]
NC
XD[14]
12
11
XOE_N
GND_IO
NC
PIOA[11]/ XA[20]
PIOA[10]/ XA[19]
VDD_ CORE
XA[12]
XA[9]
XA[3]
XA[0]
NC
VDD_IO
XD[13]
11
10
XBWE_ N[0]
XROM CS_N
XWE_N
PIOA[13]/ XA[22]
XA[17]
XA[13]
XA[11]
VDD_IO
XA[6]
XD[12]
XD[10]
GND_IO
XD[11]
10
9
XRAM CS_N
XIOCS_ N[1]
XBWE_ N[1]
XIOCS_ N[0]
XD[7]
XD[9]
XD[5]
XD[8]
9
8
GND_ CORE
VDD_ CORE
PIOB[1]/ DREQCLR 0 PIOB[3]/ DREQCLR 1
PIOB[0]/ DREQ0
XD[3]
XD[2]
XD[4]
XD[6]
8
7 TCOUT0
PIOB[4]/
VDD_IO
PIOB[2]/ DREQ1
XD[0]
XD[1]
NC
NC
7
6 XBS_N[0] PWMOUT0 TCOUT1
PIOB[7]/ 1
PIOB[6]/
PIOB[5]/
GND_IO
NC
VDD_ CORE
OSC1_N
OSC0
6
5 XCAS_N PWMOUT
PIOB[9]/
PIOB[10]/ XRAS_N
XBS_N[1]
GND_IO
EXINT3
GND_ CORE
RESET_N
5
4 XSDCS_N
PIOB[12]/
PIOB[8]/ XWAIT
PIOB[11]/ XSDCLK
VDD_IO
TCK
PIOA[2]/ CTS
PIOA[5]/ DTR
VDD_ CORE
AIN[0]
AIN[7]
EXINT0
EFIQ_N
EXINT2
4
3
NC
PIOB[13]/ XSDCKE
NC
DBGRQ
TDO
PIOA[3]/ DSR
PIOA[6]/ RTS
GND_ CORE
AIN[3]
AIN[4]
PIOA[8]/ STXD
EXINT1
PIOA[9]/ SRXD
3
2
NC
GND_IO
DBGACK
nTRST
TBE
PIOA[1]/ SOUT
PIOA[4]/ DCD
NC
AVDD
AIN[1]
AIN[6]
NC
MODE[2]
2
1
NC
PIOB[14]/ XDQM[1]/ XCAS_N[1]
PIOB[15]/ XDQM[0]/ XCAS_N[0]
TDI
TMS
PIOA[0]/ SIN
PIOA[7]/ RI
VREF
AIN[2]
AIN[5]
AGND
MODE[0]
MODE[1]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
Note: Don't connect NC pins with others.
144-Pin Plastic LFBGA
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LIST OF PINS
Pin Number
TQFP LFBGA
Primary Function Pin Name
PIOB[14] PIOB[15] DBGRQ DBGACK TDI TDO nTRST TMS TCK TBE PIOA[0] PIOA[1] PIOA[2] PIOA[3] PIOA[4] PIOA[5] PIOA[6] PIOA[7]
Secondary Function Pin Name
XDQM[1]/ XCAS_N[1] XDQM[0]/ XCAS_N[0]
I/O
Function
I/O
O O
Function
I/O mask/CAS (MSB) I/O mask/CAS (LSB)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
B1 C1 D3 C2 D1 E3 D2 E1 E4 E2 F1 F2 F4 F3 G2 G4 G3 G1 H3 H4 J2 H1 J4 K2 J1 J3 K3 K1 L2 K4 L1 M1 N1 N2 L3 N3 L4 M3 N4
I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) I O I O I I I I Debugging input signal Debugging output signal JTAG data input JTAG data output JTAG reset JTAG mode select JTAG clock Test input signal
-- -- -- -- -- -- -- --
SIN SOUT CTS DSR DCD DTR RTS RI
-- -- -- -- -- -- -- --
I O I I I O O I UART Serial Data In UART Serial Data Out UART Clear To Send UART Set Ready UART Carrier Detect UART Data Terminal Ready UART Request To Send UART Ring Indicator
I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function)
GND_CORE GND Core ground VDD_CORE AVDD VREF AIN[0] AIN[1] AIN[2] AIN[3] AIN[4] AIN[5] AIN[6] AIN[7] AGND MODE[0] MODE[1] MODE[2] PIOA[8] PIOA[9] EXINT0 EXINT1 EXINT2 VDD Core power supply VDD Analog-to-digital converter power supply I I I I I I I I I Analog-to-digital converter reference voltage Analog-to-digital converter analog input Analog-to-digital converter analog input Analog-to-digital converter analog input Analog-to-digital converter analog input Analog-to-digital converter analog input Analog-to-digital converter analog input Analog-to-digital converter analog input Analog-to-digital converter analog input
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
STXD SRXD
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
O I SIO transmit data output SIO receive data input
GND GND for A/D converter I I I Mode setting Mode setting Mode setting
I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) I I I Interrupt input Interrupt input Interrupt input
-- -- --
-- -- --
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Pin Number
TQFP LFBGA
Primary Function Pin Name
EXINT3 EFIQ_N RESET_N GND_IO
Secondary Function Pin Name I/O Function
I/O
I I I Interrupt input FIQ input Reset input
Function
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
L5 M4 N5 K5 M5 N6 M6 L6 K7 L7 L8 K8 M8 M9 N8 K9 M10 N9 L9 L10 N10 M11 K10 N11 N12 M13 L13 K11 L12 K13 J11 K12 J13 J10 J12 H13 H12 H10 H11 G12 G10 G11
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
GND I/O ground
GND_CORE GND Core ground OSC0 OSC1_N VDD_CORE XD[0] XD[1] XD[2] XD[3] XD[4] XD[5] XD[6] XD[7] GND_IO XD[8] XD[9] XD[10] XD[11] VDD_IO XD[12] XD[13] XD[14] XD[15] GND_IO XA[0] XA[1] XA[2] XA[3] XA[4] XA[5] XA[6] XA[7] XA[8] GND_IO VDD_IO XA[9] XA[10] XA[11] XA[12] I O Oscillator input Oscillator output
VDD Core power supply I/O External data bus I/O External data bus I/O External data bus I/O External data bus I/O External data bus I/O External data bus I/O External data bus I/O External data bus GND I/O ground I/O External data bus I/O External data bus I/O External data bus I/O External data bus VDD I/O power supply I/O External data bus I/O External data bus I/O External data bus I/O External data bus GND I/O ground O O O O O O O O O External address output External address output External address output External address output External address output External address output External address output External address output External address output
GND I/O ground VDD I/O power supply O O O O External address output External address output External address output External address output
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Pin Number
TQFP LFBGA
Primary Function Pin Name I/O Function Pin Name
Secondary Function I/O Function
82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
G13 F11 F10 F12 E12 F13 E10 D12 E13 E11 D11 D13 C12 D10 B12 A12 A11 C10 B11 A10 C9 B10 A9 D9 B9 A8 B8 D8 C8 B7 D7 C7 A7 C6 D6 B6 B5 A6 D5 B4 A5 C5
GND_CORE GND Core ground VDD_CORE XA[13] XA[14] XA[15] XA[16] XA[17] GND_IO XA[18] PIOA[10] PIOA[11] PIOA[12] VDD_IO PIOA[13] PIOA[14] PIOA[15] XOE_N XWE_N GND_IO XBWE_N[0] XBWE_N[1] XROMCS_N XRAMCS_N XIOCS_N[0] XIOCS_N[1] VDD Core power supply O O O O O External address output External address output External address output External address output External address output
-- -- -- -- -- -- -- -- --
XA[19] XA[20] XA[21]
-- -- -- -- -- -- -- -- --
O O O External address output External address output External address output
GND I/O ground O External address output
I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) VDD I/O power supply I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) O O Output enable (except SDRAM) Write enable
--
XA[22] XA[23] XWR
--
O O O External address output External address output External bus data transfer direction
-- -- -- -- -- -- -- -- -- --
DREQ0 DREQCLR0
-- -- -- -- -- -- -- -- -- --
I O DMA request signal (Ch 0) DREQ clear signal (Ch 0)
GND I/O ground O O O O O O Write enable (LSB) Write enable (MSB) External ROM chip select External RAM chip select I/O bank 0 chip select I/O bank 1 chip select
GND_CORE GND Core ground VDD_CORE PIOB[0] PIOB[1] VDD_IO PIOB[2] PIOB[3] PIOB[4] PIOB[5] GND_IO PIOB[6] PIOB[7] XBS_N[0] XBS_N[1] PIOB[8] PIOB[9] PIOB[10] VDD Core power supply I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) VDD I/O power supply I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) GND I/O ground I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) O O External bus byte select (LSB) External bus byte select (MSB)
--
DREQ1 DREQCLR1 TCOUT0 TCOUT1
--
I O O O DMA request signal (Ch 1) DREQ clear signal (Ch 1) DMA Termination Signal (CH 0) DMA Termination Signal (CH 1)
--
PWMOUT0 PWMOUT1
--
O O PWM output (Ch 0) PWM output (Ch 1)
-- --
XWAIT XCAS_N XRAS_N
-- --
I O O WAIT input for IO bank 0 Column address strobe (SDRAM) Row address strobe (SDRAM/EDO)
I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function)
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Pin Number
TQFP LFBGA
Primary Function Pin Name
PIOB[11] PIOB[12] PIOB[13] VDD_IO GND_IO
Secondary Function Pin Name
XSDCLK XSDCS_N XSDCKE
I/O
Function
I/O
O O O
Function
SDRAM clock SDRAM chip select Clock enable (SDRAM)
124 125 126 127 128
C4 A4 B3 D4 B2
I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) I/O General-purpose port (with interrupt function) VDD I/O power supply GND I/O ground
-- --
-- --
Note: A1, C3, H2, M2, K6, M7, N7, M12, N13, L11, C13, B13, A13, C11, A3, A2 pins of LFBGA packaged version are NC pins. These pins must be left unconnected.
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PIN DESCRIPTION
Pin Name System
RESET_N OSC0 I I Reset input Crystal oscillator connection or external clock input. Connect a crystal oscillator (16 MHz to 33 MHz), if used, to OSC0 and OSC1_N. Crystal oscillator connection. Leave this pin unconnected if using external clock input. Test pin. Drive at High level. -- -- Negative
I/O
Description
Primary/ Secondary
Logic
OSC1_N TBE
O I
-- -- Negative
Debugging support.
DBGRQ DBGACK TCK TMS nTRST TDI TDO I O I I I I O Debugging pin. Normally connect to ground. Debugging pin. Normally leave open. Debugging pin. Normally connect to ground. Debugging pin. Normally drive at High level. Debugging pin. Normally connect to ground. Debugging pin. Normally drive at High level. Debugging pin. Normally leave open. General-purpose port. Not available for use as port pins when secondary functions are in use. General-purpose port. Not available for use as port pins when secondary functions are in use. Note that enabling DRAM controller with MODE[2:0] inputs permanently configures PIOB[15:9] for their secondary functions, making them unavailable for use as port pins. -- -- -- -- -- -- -- Positive Positive -- Positive Negative Positive Positive
General-purpose I/O ports
PIOA[15:0] I/O Primary Positive
PIOB[15:0]
I/O
Primary
Positive
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Pin Name External Bus
XA[23:19]
I/O
Description
Primary/ Secondary
Logic
O
Address bus to external RAM, external ROM, external I/O banks, and external DRAM. After a reset, these pins are configured for their primary function (PIOA[14:10]). Address bus to external RAM, external ROM, external I/O banks, and external DRAM Data bus to external RAM, external ROM, external I/O banks, and external DRAM ROM bank chip select SRAM bank chip select I/O bank 0 chip select I/O bank 1 chip select Output enable/read enable Write enable Byte select: XBS_N[1] for MSB; XBS_N[0] for LSB LSB write enable MSB write enable Data transfer direction for external bus, used when connecting to Motorola I/O devices. This represents the secondary function of pin PIOA[15], produced by setting bit 7 in the port control (GPCTL) register to "1." External I/O bank 0 WAIT signal. This input permits access to devices slower than register settings. Row address strobe. Used for both EDO DRAM and SDRAM. Column address strobe signal (SDRAM) SDRAM clock (same frequency as internal system clock) Clock enable (SDRAM) Chip select (SDRAM) Connected to SDRAM: DQM (MSB) Connected to EDO DRAM: column address strobe signal (MSB) Connected to SDRAM: DQM (LSB) Connected to EDO DRAM: column address strobe signal (LSB)
Secondary
Positive
XA[18:0] XD[15:0]
O I/O
-- --
Positive Positive
External bus control signals
XROMCS_N XRAMCS_N XIOCS_N[0] XIOCS_N[1] XOE_N XWE_N XBS_N[1:0] XBWE_N[0] XBWE_N[1] XWR O O O O O O O O O O -- -- -- -- -- -- -- -- -- Secondary Negative Negative Negative Negative Negative Negative Negative Negative Negative --
XWAIT
I
Secondary
Positive
External bus control signals (DRAM)
XRAS_N XCAS_N XSDCLK XSDCKE XSDCS_N XDQM[1]/ XCAS_N[1] XDQM[0]/ XCAS_N[0] O O O O O O O Secondary Secondary Secondary Secondary Secondary Secondary Secondary Negative Negative -- -- Negative Positive/ Negative Positive/ Negative
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Pin Name
I/O
Description
Primary/ Secondary
Logic
DMA control signals
DREQ0 DREQCLR0 TCOUT0 DREQ1 DREQCLR1 TCOUT1 I O O I O O Ch 0 DMA request signal, used when DMA controller configured for DREQ type Ch 0 DREQ signal clear request. The DMA device responds to this output by negating DREQ. Indicates to Ch 0 DMA device that last transfer has started Ch 1 DMA request signal, used when DMA controller configured for DREQ type Ch 1 DREQ signal clear request. The DMA device responds to this output by negating DREQ. Indicates to Ch 1 DMA device that last transfer has started Secondary Secondary Secondary Secondary Secondary Secondary Positive Positive Positive Positive Positive Positive
SIO
STXD SRXD O I SIO transmit signal SIO receive signal Secondary Secondary Positive Positive
UART
SIN SOUT CTS I O I Serial data input Serial data output Clear To Send. Indicates that modem or data set is ready to transfer data. Bit 4 in modem status register reflects this input. Data Set Ready. Indicates that modem or data set is ready to establish a communications link with UART. Bit 5 in modem status register reflects this input. Data Carrier Detect. Indicates that modem or data set has detected data carrier signal. Bit 7 in modem status register reflects this input. Data Terminal Ready. Indicates that UART is ready to establish a communications link with modem or data set. Bit 0 in modem control register controls this output. Request To Send. Indicates that UART is ready to transfer data to modem or data set. Bit 1 in modem control register controls this output. Ring Indicator. Indicates that modem or data set has received telephone ring indicator. Bit 6 in modem status register reflects this input. Secondary Secondary Secondary Positive Positive Negative
DSR
I
Secondary
Negative
DCD
I
Secondary
Negative
DTR
O
Secondary
Negative
RTS
O
Secondary
Negative
RI
I
Secondary
Negative
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FEDL674000-02
OKI Semiconductor
ML674000
Pin Name PWM signals
PWMOUT0 PWMOUT1
I/O
Description
Primary/ Secondary
Secondary Secondary
Logic
O O
Ch 0 PWM output Ch 1 PWM output
Positive Positive
Analog-to-digital converter
AIN[0] AIN[1] AIN[2] AIN[3] AIN[4] AIN[5] AIN[6] AIN[7] VREF AVDD AGND I I I I I I I I I Ch 0 analog input Ch 1 analog input Ch 2 analog input Ch 3 analog input Ch 4 analog input Ch 5 analog input Ch 6 analog input Ch 7 analog input Analog-to-digital converter convert reference voltage Analog-to-digital converter power supply Analog-to-digital converter ground -- -- -- -- -- -- -- -- -- -- --
Interrupt signals
EXINT3 EXINT2 EXINT1 EXINT0 EFIQ_N I External interrupt input signals -- Positive/ Negative
I
External fast interrupt input signal. Interrupt controller connects this to CPU FIQ input. Operating mode control signals
--
Negative
MODE
MODE[2:0] I --
Power supplies
VDD_CORE VDD_IO GND_CORE GND_IO -- -- -- -- Core power supply I/O power supply Core ground I/O ground -- -- -- --
13/24
FEDL674000-02
OKI Semiconductor
ML674000
DESCRIPTION OF FUNCTIONS
CPU CPU core: Operating frequency: Instructions: General register bank: Built-in barrel shifter: Multiplier: Built-in debug function: Built-in Memory RAM: ARM7TDMI 1 MHz to 33 MHz ARM instruction (32-bit length) and Thumb instruction (16-bit length) can be mixed. 31 x 32 bits ALU and barrel shift operations can be executed by one instruction. 32 bits x 8 bits (Modified Booth's Algorithm) JTAG interface, break point register 8 KB (2K x 32 bits) Connected to processor bus (read: 1 cycle access, write: 2 cycle access)
Interrupt Controller Fast interrupt input (FIQ) and interrupt input (IRQ) are employed as interrupt input signals of ARM core. The interrupt controller controls these interrupt signals going to ARM core. (1) Interrupt sources of ML674000 FIQ: 1 source, external source (external pin: EFIQ_N) IRQ: 23 sources, internal sources : 19, external sources : 4 (external pins: EXINT[3:0]) (2) Interrupt priority level Priority can be set in 8 levels for each source. (3) External interrupt pin input Level sense: Interrupt signal level is selected. Edge sense: Rise or fall is selected. (4) External fast interrupt pin input Edge sense: Fall edge is detected. Timer 7 channels of 16-bit reload timers are employed. Of these, 1 channel is used as system timer for OS. The timers of other 6 channels are used in application software. (1) System timer: 1 channel 16-bit auto reload timer: Used as system timer for OS (This timer is incorporated in PLAT-7B.) Interval mode (2) Application timer: 6 channels 16-bit auto reload timer One shot, interval mode Clock can be set for each channel WDT This MCU contains a Watch Dog Timer that can also function as an interval timer. (1) 16-bit timer (2) Watch dog timer or interval timer mode can be selected (3) Interrupt or reset generation - Watchdog timer mode: generates reset or interrupt when the timer is overflows. - Interval timer mode: generates interrupt when the timer reaches an overflow condition. (4) Maximum period: 200 msec or longer
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FEDL674000-02
OKI Semiconductor
ML674000
PWM This MCU contains two PWM (Pulse Width Modulation) channels which can change duty cycle within a certain fixed period. The PWM output resolution is 16 bits for each channel. Serial Interface This LSI contains two channels of serial interface. (1) UART without FIFO: 1 channel This serial interface is incorporated in PLAT-7B. (2) UART with 16-byte FIFO: 1 channel This is ACE (Asynchronous Communication Element) equivalent in function to 16550A. It has 16-byte FIFO in both sending and receiving. GPIO This LSI contains two 16-bit parallel ports. (1) (2) (3) (4) Input or output can be selected for each bit. Interrupt can be used for all 16 bits of each channel, and all GPIO pins can be used as interrupt inputs. Interrupt mask and interrupt mode (level) can be set for all bits. Configured as inputs immediately after reset.
AD Converter This is a successive approximation type AD converter. (1) (2) (3) (4) (5) 10 bits x 8 channels Sample and hold function Scan mode and select mode are supported Interrupt is generated after completion of conversion. Minimum conversion time of 5 s.
DMAC This MCU contains a two channel direct memory access controller which transfers data between memory and memory, between I/O and memory and between I/O and I/O. (1) Number of channels: 2 channels (2) Channel priority level: Fixed mode Channel priority level is always fixed (channel 0 > 1). Roundrobin Priority level of the channel requested for transfer is kept lowest. (3) Maximum number of transfers: 65,536 times (64K times) (4) Data transfer size: Byte (8 bits), half-word (16 bits), word (32 bits) (5) Bus request system: Cycle steal mode Bus request signal is asserted for each DMA transfer cycle. Burst mode Bus request signal is asserted until all transfers of transfer cycles are complete. (6) DMA transfer request: Software request By setting the software transfer request bit inside DMAC, the CPU starts DMA transfer. External request DMA transfer is started by external request allocated to each channel. (7) Interrupt request: Interrupt request is generated in CPU after the end of DMA transfers for the set number of transfer cycles or after occurrence of error. Interrupt request signal is output separately for each channel. Interrupt request signal output can be masked for each channel.
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FEDL674000-02
OKI Semiconductor
ML674000
External Memory Controller Controls access of externally connected devices such as ROM (FLASH), SRAM, SDRAM (EDO DRAM) and IO devices. (1) ROM (FLASH) access function Supports 16-bit device Supports FLASH memory: Byte write (can be written only by IF equivalent to SRAM). Access timing setting (2) SRAM access function Supports 16-bit device Supports asynchronous SRAM Access timing setting (3) DRAM access function Supports 16-bit device Supports EDO/SDRAM: Simultaneous connections to EDO-DRAM and SDRAM cannot be made. Access timing setting (4) External IO access function Supports 8-bit/16-bit device Supports 2 banks independently Supports external wait input: XWAIT (IO bank 0 only) Access timing setting (for each bank) Power Management HALT and STANDBY functions are supported as power save functions. (1) HALT mode HALT object CPU, internal RAM, AHB bus control HALT mode setting: Set by the system control register. HALT mode cancelling: Reset, interrupt (2) STANDBY mode Stops the clock of entire LSI. STANDBY mode setting: Specified by the system control register. STANDBY mode cancelling: Reset, external interrupt (other than FIQ)
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FEDL674000-02
OKI Semiconductor
ML674000
ABSOLUTE MAXIMUM RATINGS
Item Digital power supply voltage (core) Digital power supply voltage (I/O) Input voltage Output voltage Analog power supply voltage Analog reference voltage Analog input voltage Input current High level output current Low level output current *1 Low level output current *2 Power dissipation Storage temperature Symbol VDD_CORE VDD_IO VI VO AVDD VREF VAI II IOH IOL PD TSTG Ta = 85C per package -- GND = AGND = 0 V Ta = 25C Conditions Rating -0.3 to +3.6 -0.3 to +4.6 -0.3 to VDD_IO+0.3 -0.3 to VDD_IO+0.3 -0.3 to VDD_IO+0.3 -0.3 to VDD_IO+0.3 and -0.3 to AVDD +0.3 -0.3 to VREF -10 to +10 +10 -20 -30 530 -50 to +150 mW C mA V Unit
Notes 1. All output pins except XA[15:0] 2. XA[15:0]
RECOMMENDED OPERATING CONDITIONS
(GND = 0 V) Item Digital power supply voltage (core) Digital power supply voltage (I/O) Analog power supply voltage Analog reference voltage Storage hold voltage Operating frequency Ambient temperature Symbol VDD_CORE VDD_IO VDD_CORE VDD_IO AVDD VREF VDDH fOSC Ta AVDD = VDD_IO VREF = AVDD = VDD_IO fOSC = 0 Hz VDD_CORE = 2.25 to 2.75 VDD_IO = 3.0 to 3.6 * -- 3.0 3.0 3.0 2.25 1 -40 3.3 3.3 3.3 -- -- 25 3.6 3.6 3.6 3.6 33.333 +85 MHz C V Conditions Minimum 2.25 Typical 2.5 Maximum 2.75 Unit
Note Oscillator frequencies between 16 MHz and 33 MHz. Minimum of 2.56 MHz for external SDRAM. Minimum of 6.4 MHz for external EDO DRAM. Minimum of 2 MHz for analog-to-digital converter.
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FEDL674000-02
OKI Semiconductor
ML674000
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD_CORE = 2.25 to 2.75V, VDD_IO = 3.0 to 3.6V, Ta = -40 to +85C) Item High level input voltage Low level input voltage Schmitt input buffer threshold voltage High level output voltage Low level output voltage Low level output voltage *1 Low level output voltage *2 Input leak current *3 Input leak current *4 Output leak current Input pin capacitance Output pin capacitance I/O pin capacitance Analog reference power supply current Current consumption (STANDBY) Current consumption (HALT) *7 Current consumption (RUN) IIH/IIL ILO CI CO CIO IREF VOL Symbol VIH VIL VT+ VT- VHYS VOH IOH = -100 A IOH = -4 mA IOL = 100 A IOL = 4 mA IOL = 6 mA VI = 0 V/VDD_IO VI = 0 V Pull-up resistance of 50 k VO = 0 V/VDD_IO -- -- -- Analog-to-digital converter operative *5 Analog-to-digital converter stopped Ta = 25C *
6
Conditions
Minimum 2.0 -0.3
Typical -- -- 1.6 1.1 0.5 -- -- -- -- -- -- 66 -- 6 9 10 320 1 3 1 8 2 15 18
Maximum VDD_IO+0.3 0.8 2.1 -- -- -- -- 0.2 0.4 0.4 10 200 10 -- -- -- 650
Unit
--
-- 0.7 0.4 VDD-0.2 2.4 -- -- -- -10 10 -10 -- -- -- -- -- -- -- -- -- -- --
V
A
pF
A 2 45 5 15 5 25 30 A mA mA
IDDS_CORE IDDS_IO IDDH_CORE IDDH_IO IDD_CORE IDD_IO
fOSC = 16 MHz CL = 50 pF
Notes 1. All output pins except XA[15:0] 2. XA[15:0] 3. All input pins except RESET_N 4. RESET_N pin, with 50 k pull-up resistance 5. Analog-Digital Converter operation ratio is 20% 6. VDD_IO or 0 V for input ports; no load for other pins 7. DRAM function stop by MODE pin setting
18/24
FEDL674000-02
OKI Semiconductor
ML674000
Power Consumption The values in the following charts are measured values in the operating conditions indicated. The samples were taken during normal operation in ARM mode with all peripheral clocks activated. Instructions were being executed from external memory.
IDD_CORE -f
50 45 40 35 30 25 20 15 10 5 0 0
IDD_IO -f
50 45 40 35 30 25 20 15 10 5 0 0
Ta=25C
VDD_CORE=2.75V VDD_CORE=2.5V VDD_CORE=2.25V
Ta=25C CL=50pF
VDD_IO=3.6V VDD_IO=3.3V VDD_IO=3V
IDD_CORE (mA)
5
10
15
20
25
30
35
IDD_IO (mA)
5
10
15
20
25
30
35
f(MHz)
f(MHz)
IDD_CORE -Ta
30 25
IDD_IO -Ta
30 25
f=16MHz IDD_IO (mA)
VDD_CORE=2.75V VDD_CORE=2.5V VDD_CORE=2.25V
f=16MHz CL=50pF
VDD_IO=3.6V VDD_IO=3.3V VDD_IO=3V
IDD_CORE (mA)
20 15 10 5 0 -50 -25 0 25 50 75
20 15 10 5 0
100
-50
-25
0
25
50
75
100
Ta(C)
Ta(C)
19/24
FEDL674000-02
OKI Semiconductor
ML674000
Analog-to-Digital Converter Characteristics
(VDD_CORE = 2.50 V, VDD_IO = 3.3 V, Ta = 25C) Item Resolution Linearity error Differential linearity error Zero scale error Full scale error Conversion time Throughput Symbol n EL ED EZS EFS tCONV Conditions -- Analog input source impedance Ri 1k -- -- Minimum Typical Maximum -- -- -- -- -- 5 10 -- 3 3 3 3 -- -- 10 -- -- -- -- -- 200 s kHz LSB Unit bit
Note: VDD_IO and AVDD should be supplied separately. * Definition of Terms (1) Resolution: Minimum input analog value recognized. For 10-bit resolution, this is (VREF - Aground) / 1024. (2) Linearity error: Difference between the theoretical and actual conversion characteristics. (Note that it does not include quantization error.) The theoretical conversion characteristic divides the voltage range between VREF and AGND into 1024 equal steps. (3) Differential linearity error: Difference between the theoretical and actual input voltage change producing a 1-bit change in the digital output anywhere within the conversion range. This is an indicator of conversion characteristic smoothness. The theoretical value is (VREF - Aground) / 1024. (4) Zero scale error: Difference between the theoretical and actual conversion characteristics at the point where the digital output switches from "0x000" to "0x001." (5) Full scale error: Difference between the theoretical and actual conversion characteristics at the point where the digital output switches from "0x3FE" to "0x3FF."
20/24
FEDL674000-02
OKI Semiconductor
ML674000
PACKAGE DIMENSIONS
(Unit : mm)
TQFP128-P-1414-0.40-K
Mirror finish
5
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.55 TYP. 1/Nov. 18, 1999
21/24
FEDL674000-02
OKI Semiconductor
ML674000
Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL674000-02
OKI Semiconductor
ML674000
REVISION HISTORY
Document No.
PEDL674000-01
Date
Oct., 2001
Page Previous Current Edition Edition
- - 1 - - 1 2-12 13-15 16-37 - 1 8 8 15-50 -
Description
Preliminary edition 1 Preliminary edition 2 Feature Table rewritten. Pin names are changed. Description rewritten. Electrical characteristics added. Final edition 1 Number of interrupt sources corrected. TBE signal description corrected. Pin numbers of XA[23:19] and XA[18:0] corrected. Description rewritten. Final edition 2 Description changed. Supported DRAM area changed from 16Mbytes to 64Mbytes. Add 144-pin LFBGA package. Add Pin layout for LFBGA package. Change table of pin list. (Add LFBGA description and correct some misdescription.) Change table of pin description. (Correct some misdescription.) Description changed. Description of AC characteristics Deleted. Please refer to User's Manual. The values of Zero scale error and Full scale error of Analog-to-Digital converter are corrected. Add Package Dimensions for LFBGA package.
PEDL674000-02
May 17, 2002
2-13 14-16 17 - 1
FEDL674000-01
Aug. 8, 2002
8 8 15-36 -
1
1 to 2
- 4 to 7 FEDL674000-02 Dec. 10, 2002 8 to 11 12 to 14 18 to 50 51 -
5 6 to 9 10 to 13 14 to 16 - 21 23
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FEDL674000-02
OKI Semiconductor
ML674000
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd.
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